An SVPWM Scheme for the Suppression of Zero-Sequence Current in a Four-Level Open-End Winding Induction Motor Drive With Nested Rectifier-Inverter

Abstract

A four-level open-end winding induction motor (OEWIM) drive is known to suffer from two perennial problems. One is the problem of zero-sequence current in the motor phases, which is caused by the existence of zero sequence voltage in them. The other is the overcharging of the dc-link capacitor of the inverter operated with lower dc-link voltage by its counterpart operated with a higher dc-link voltage. This paper investigates the applicability of a special variant of space vector pulse width modulation (SVPWM) scheme for a recently proposed power circuit configuration, in which a rectifier–inverter combination is nested within the conventional two-level inverter configu ration to achieve four-level inversion. This PWM scheme is named as the sample-averaged zero-sequence elimina tion (SAZE) SVPWM scheme, wherein the zero sequence voltage is suppressed in each sampling time period in the average sense. Both of the aforementioned problems encountered in this drive are successfully overcome for this power circuit configuration by resorting to the pro posed SVPWM strategy