A new structure of three-phase five-level inverter with nested two-level cells

Abstract

This paper presents a new structure of three‐phase five‐level inverter with a single direct current (DC) source for low‐ and medium‐voltage applications. The proposed configuration is built with a cascade connection of two‐level cells in a nested form and owns the advantages of a reduced number of passive com ponents, total blocking voltage of the switches, and isolated DC sources. In order to make this topology attractive, a comparison is made with five‐level inverter topologies proposed for low‐ and medium‐voltage applications in recent years. The proposed circuit is powered using a single DC source and an auxiliary voltage‐balancing circuit (AVBC) to maintain the desired DC link capacitor voltages. A sinusoidal pulse width modulation (SPWM) scheme is implemented in field‐programmable gate array (FPGA), using Xilinx blocks developed in MATLAB/SIMULINK environment, to control the inverter switches. The performance of the proposed topology is verified through MATLAB simulation and prototype model for a step change in load. Finally, the experimental results are presented to validate the effectiveness of the pro posed topology.