A Seven-Level VSI with a Front-End Cascaded Three-Level Inverter and Flying-Capacitor-Fed H-Bridge

Abstract

Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewableenergysourceswiththegridandseveralindustrialdrive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level in verter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with f lyingcapacitors(FCs).Thispaperpresentstheoperatingprinciple and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposedcircuitconfigurationandtheirvoltageratingsareconsid erably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique.