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http://localhost:8080/xmlui/handle/123456789/3756Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Arunprasath, R. | - |
| dc.contributor.author | Vijayakumar, D. | - |
| dc.contributor.author | Rathinakumar, M. | - |
| dc.contributor.author | Meikandasivam, S. | - |
| dc.contributor.author | Kirubakaran, A. | - |
| dc.date.accessioned | 2025-12-29T09:28:57Z | - |
| dc.date.available | 2025-12-29T09:28:57Z | - |
| dc.date.issued | 2019 | - |
| dc.identifier.citation | 10.35940/ijeat.A9843.109119 | en_US |
| dc.identifier.uri | http://localhost:8080/xmlui/handle/123456789/3756 | - |
| dc.description | NITW | en_US |
| dc.description.abstract | In this paper, a modified structure of two-stage sepic based five-level T-type inverter is presented for photovoltaic applications. The proposed topology consists of a frond-end sepic converter cascaded with full bridge T-type inverter through a high-frequency transformer. The proposed topology owns the merits of high boost output voltage level, modularity, reduced device parts, and better quality of supply. Therefore, a detailed operation of the proposed topology and the level generations using sine pulse width modulation are presented. Finally, the performance of the proposed topology is validated through Matlab simulation and experimental prototype model results. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | International Journal of Engineering and Advanced Technology | en_US |
| dc.subject | Field programmable gate array (FPGA) | en_US |
| dc.subject | Multilevel inverter | en_US |
| dc.title | Modified structure of sepic based single-phase five-level t-type inverter for photovoltaic applications | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Electrical Engineering | |
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