High Speed and Area-Time E cient Finite eld GF(2m) Point Multiplication Architectures for Elliptic Curve Cryptographic Applications

Abstract

Advances in communication technology and availability of high bandwidth enables billions of devices communicate condential information over the Internet. Hence, it is required to introduce some data security technique while transmitting the information which can be addressed using various cryptographic algorithms. Cryptography is one of the profound technique used to secure the data by employ ing encryption and decryption algorithms. Over the last few years, technological ad vances in the implementation of smart sensors, processing elements and communication services in resource-constrained devices have enabled the rapid growth and emergence of evolving technologies like Wireless sensor-networks (WSNs) and Internet-of-Things (IoT). These technologies elevated the need for e cient and high-performance crypto graphic algorithms. The hardware realization of these algorithms involve the selection of an appropriate architecture with constraints on area, speed and power. The conven tional approaches such as Elgamal, and RSA are found to be impractical to implement on resource constrained devices. The Elliptic Curve-Cryptography (ECC) suggested by Koblitz and Miller has captivated considerable attention when compared to similar cryp tosystems available in the literature owing to its high security per bit ratio and small key size. The performance of ECC relies on point multiplication operation and its underly ing nite eld operations. Each point multiplication operation is realized by a series of nite- eld addition, nite- eld inversion and nite- eld multiplication operations. FF multiplication and FF-inversion are the two area and time critical operations in point multiplication. Hence, the e ciency of point multiplication relies on e ciency of these two nite eld operations. In addition, the type of irreducible polynomial used also im pacts the performance of point multiplication architecture. Many high performance point multiplication architectures for various classes of irreducible polynomials using polynomial Abstract basis are proposed in the literature to achieve reduction in area and time complexities. In this thesis, we focus on the design of area-time e cient hardware architectures for point multiplication targeting the implementation of security in ECC applications. Ac cordingly, some GF(2m) point multiplication algorithms and formulations are proposed based on the available algorithms in the literature and subsequently e cient point mul tiplication architectures are realized for these proposed algorithms. We rst studied the e cient implementation of FF-inversion and FF-multiplication operations. We proposed a FF-inversion architecture over GF(2m) for general irreducible polynomials based on the Itoh-Tsujii algorithm. We then proposed an area-time e cient point multiplication ar chitecture employing the proposed FF-inversion architecture. In addition, a digit-serial FF-multiplier and parallel Itoh-Tsujii algorithm for inversion are proposed to reduce the computation time. An area-time e cient and high speed point multiplication architec tures are proposed by employing the proposed FF-multiplier and FF-inversion modules. Adetailed analysis of the possible parallelization and scheduling schemes employed to re duce the latency of proposed point multiplication architectures is presented. The area and time complexities of all the proposed architectures are computed analytically for various m values and compared with similar architectures in the literature. It is observed from the comparison of the results that the proposed architectures outperform the existing ar chitectures in terms of area-time complexities. These proposed area-time e cient GF(2m) point multiplication architectures can be preferred in the implementation of security in ECC applications