Design and Implementation of Compact High Performance On-chip Multilayer IPD Inductors for 5G Applications

Abstract

Today’s information centric world is witnessing a massive 5G proliferation, with an explosion of 5G devices in multitude of 5G applications like mobile cellular networks, Wireless local area network (WLAN), Internet of Things (IOT), smart systems, Vehicle to Vehicle (V2V), Machine to machine (M2M), Global Positioning System (GPS) navigation etc. Spectacular growth and worldwide deployment of 5G communication networks, spurred the need to design and develop very compact and yet high-performance on-chip passive inductors and capacitors, which facilitate the co-location of analog and digital components on the same chip. In literature, successful radio frequency front end (RFFE) circuits prominently used the low-cost Complementary Metal oxide Semiconductor (CMOS) technology. Integrated Passive Device (IPD) technology based on-chip inductors and capacitors became indispensable, beyond 1 GHz due to their noise and power advantages. On-chip IPD passives play vital role in the miniaturization of the key performance deciders like voltage control oscillator (VCO), low noise amplifier (LNA), bandpass filter (BPF). Offchip IPD technology easily integrates with CMOS 5G radio frequency integrated circuits (RFIC) and system on-chip (SOC) to realize the low-cost 5G RFFE circuits. The design of on-chip passives need trade-off between the cost of technology provisions and application demands, posing several challenges like design complexity, high quality factor, least on-chip area and fabrication costs. The spiral geometry passives became attractive as they exhibit large values of inductance, capacitance and moderate quality factors. In this thesis, the attractive multilayer spiral geometry is adopted not only to obtain larger values of inductance, self-resonant frequency (SRF) and quality factor (Q), but also to reduce the size of on-chip passive components. The multilayer inductor structure is developed based on vertical stacking concept (multilevel) of metal layers. Initially, the constant width and variable width series stacked spiral inductors are proposed. The variable width of the metal decreases the series resistance and series stacking increases the metal trace length. It also helps to reduce the skin and proximity effects and up down series stacking reduces the parasitic capacitance. Thus, it attains high Q and inductance over the standard planar inductor. A novel series stacked double-split structure is proposed to split the conductor metal path in all the layers. Optimal selection of the double-split track width xi helps to reduce the skin and proximity effects, overall parasitic capacitance. Thus increases the Q value and SRF of the inductors. In this thesis, a planar spiral capacitor is developed in single layer. The sensitivity analysis of spiral capacitor gives a trade-off between electrical response and layout parameters. Mathematical validation of on-chip passives is a key mechanism to justify the validity of proposed models. Frequency dependent and independent analytical expressions used to extract the inductance value, show much deviation in the extracted inductance values at 5G frequencies. Numerically solved integral equations yielded smaller error. The proposed IPD inductors and capacitor are used in the implementation of LNAs and BPFs for 5G applications. A narrow band 5GHz LNA is implemented by using the proposed IPD ML series stacked double-split inductor and standard inductor. Also two 5G bandpass filters at 8.2 GHz and 25 GHz are designed, simulated, fabricated and tested using proposed IPD inductors and capacitor to validate the simulation results. Design and simulation of the proposed inductors and their applications are carried out by using High-Frequency Structural Simulator (HFSS), Advanced Design System (ADS), and Sonnet EM simulator. As fabrication facility on silicon substrate is not available, the proposed IPD inductors and capacitor are scaled down from GHz to MHz level (scaled up dimensionally from μm to mm level). They are fabricated on FR4 substrate for PCB manufacturing and testing of respective LNA and BPF performance. The proposed novel series stacked double-split multilayer IPD spiral inductors at different 5G frequencies had exhibited 325% improvement in inductance and a 68% increase in quality factor value for the equivalent on-chip area 0.0324 mm2 compared to the standard spiral inductor at 5.5 GHz. The proposed novel double-split IPD inductor based LNA has improved the parameters like S11, S21, NF and Stability by 64%, 75%, 74%, and 129% respectively, over the CMOS Inductor. An 8.2 GHz BPF employing the proposed double-split IPD inductor has enhanced the loaded Q, S11 and S12, by 242%, 30.7%, and 85% respectively, over a similar UWB filter. The results from simulations performed, are in very good concurrence with the experimental results for all IPD inductors and capacitor. Hence, this performance equivalence has successfully validated the supremacy of the proposed very compact IPD inductors for 5G applications.