An Efficient Architecture for H.264 Intra Prediction Mode Decision Algorithm

Abstract

The paper presents an intra prediction hardware architecture where it exploits parallelism in predicting the pixels and pipelining is implemented during the calculation of the cost function. The parallelism feature includes an optimized data path which calculates only 24 unique pixel values and the former are assigned to the current macro block depending on the equations for different modes as defined in the H.264 standard. Synthesis results confirmed that the proposed architecture is able to process SD 1280×720P @ 50 fps when operating at 57 MHz for ASIC platforms.