FPGA implementation of digital down converter using CORDIC algorithm

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DC Field	Value	Language
dc.contributor.author	Agarwal, Ashok	-
dc.contributor.author	Lakshmi, Boppana	-
dc.date.accessioned	2025-01-27T05:43:52Z	-
dc.date.available	2025-01-27T05:43:52Z	-
dc.date.issued	2013	-
dc.identifier.citation	10.1117/12.2012307	en_US
dc.identifier.uri	http://localhost:8080/xmlui/handle/123456789/2955	-
dc.description	NITW	en_US
dc.description.abstract	In radio receivers, Digital Down Converters (DDC) are used to translate the signal from Intermediate Frequency level to baseband. It also decimates the oversampled signal to a lower sample rate, eliminating the need of a high end digital signal processors. In this paper we have implemented architecture for DDC employing CORDIC algorithm, which down converts an IF signal of 70MHz (3G) to 200 KHz baseband GSM signal, with an SFDR greater than 100dB. The implemented architecture reduces the hardware resource requirements by 15 percent when compared with other architecture available in the literature due to elimination of explicit multipliers and a quadrature phase shifter for mixing	en_US
dc.language.iso	en	en_US
dc.publisher	Proceedings of SPIE - The International Society for Optical Engineering	en_US
dc.subject	CORDIC,	en_US
dc.subject	Digital Down Converter,	en_US
dc.title	FPGA implementation of digital down converter using CORDIC algorithm	en_US
dc.type	Other	en_US
Appears in Collections:	Electronics and Communication Engineering

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