Multi-layer on-chip inductor for 10–100 GHz frequency applications

Abstract

A multi-layer inductor is proposed to achieve high inductance with moderate Q-factor values. The development of integration of devices technology in radio-frequency (RF) has increased the importance of on-chip inductors. In the literature, the planar inductor, the threedimensional (3D) inductor with constant width and the 3D inductor with variable width are reported. Using the basic concept of multilayer technology in very large-scale integration (VLSI) system design and considering lambda rules, the proposed inductor is designed. The inductance of the proposed inductor is nearly 37–45% higher compared with reported inductors with a moderate quality factor. This inductor is realised using 180 nm scale technology with an area of cross-section 10 × 10 µm2 . Results are presented using the IE3D EM field solver with the help of series RL and shunt RC lumped Pi model.