A Low Phase Noise 10-G bits/s Clock and Data Recovery Circuit with Modified D Latch For Backplane Applications Using Dual Loop Architecture

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DC Field	Value	Language
dc.contributor.author	Sharma, D Pavan Kumar	-
dc.contributor.author	Rao, Patri Sreehari	-
dc.contributor.author	Krishna Prasad, KSR	-
dc.date.accessioned	2025-01-09T10:14:52Z	-
dc.date.available	2025-01-09T10:14:52Z	-
dc.date.issued	2015	-
dc.identifier.citation	10.1109/ICAECC.2014.7002417	en_US
dc.identifier.uri	http://localhost:8080/xmlui/handle/123456789/2646	-
dc.description	NITW	en_US
dc.description.abstract	In this paper a clock and data recovery circuit (CDR) with modified D latch is designed meeting the standards of 10 Base-KR standard backplane. The designed circuit employs dual loop architecture in 0.18μm UMC CMOS technology. The simulated results indicate a phase noise of voltage controlled oscillator (VCO) as -173.782dBC/HZ, VCO gain of 350MHz/V while consuming 85mW from 1.8V supply. LC oscillator is designed for achieving low jitter.	en_US
dc.language.iso	en	en_US
dc.publisher	2014 International Conference on Advances in Electronics, Computers and Communications, ICAECC 2014	en_US
dc.subject	Phase locked loop	en_US
dc.subject	Phase noise	en_US
dc.title	A Low Phase Noise 10-G bits/s Clock and Data Recovery Circuit with Modified D Latch For Backplane Applications Using Dual Loop Architecture	en_US
dc.type	Other	en_US
Appears in Collections:	Electronics and Communication Engineering

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