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http://localhost:8080/xmlui/handle/123456789/2646| Title: | A Low Phase Noise 10-G bits/s Clock and Data Recovery Circuit with Modified D Latch For Backplane Applications Using Dual Loop Architecture |
| Authors: | Sharma, D Pavan Kumar Rao, Patri Sreehari Krishna Prasad, KSR |
| Keywords: | Phase locked loop Phase noise |
| Issue Date: | 2015 |
| Publisher: | 2014 International Conference on Advances in Electronics, Computers and Communications, ICAECC 2014 |
| Citation: | 10.1109/ICAECC.2014.7002417 |
| Abstract: | In this paper a clock and data recovery circuit (CDR) with modified D latch is designed meeting the standards of 10 Base-KR standard backplane. The designed circuit employs dual loop architecture in 0.18μm UMC CMOS technology. The simulated results indicate a phase noise of voltage controlled oscillator (VCO) as -173.782dBC/HZ, VCO gain of 350MHz/V while consuming 85mW from 1.8V supply. LC oscillator is designed for achieving low jitter. |
| Description: | NITW |
| URI: | http://localhost:8080/xmlui/handle/123456789/2646 |
| Appears in Collections: | Electronics and Communication Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| A_low_phase_noise_10-G_bits_s_clock_and_data_recovery_circuit_with_modified_D_latch_for_backplane_applications_using_dual_loop_architecture.pdf | 1.39 MB | Adobe PDF | View/Open |
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