Please use this identifier to cite or link to this item: http://localhost:8080/xmlui/handle/123456789/2565
Title: Variable gate oxide thickness MOSFET: A device level solution for sub-threshold leakage current reduction
Authors: Keerti Kumar, K.
Bheema Rao, N.
Keywords: Logic gates
MOSFET circuits
Lead
CMOS technology
Issue Date: Mar-2012
Publisher: 2012 International Conference on Devices, Circuits and Systems (ICDCS)
Citation: 10.1109/ICDCSyst.2012.6188765
Abstract: Scaling down in the MOSFET technology has been the important factor for continuous advancement in the semiconductor industry. As the technology scaling is entering the nanometer regime, one of the prominent features which come into the scenario are the short-channel effects (SCEs). Because of the SCEs, subthreshold leakage current has been the serious problem being faced by the scaled devices. At the device level, channel engineering and the threshold voltage lowering are the methods which were followed to control the subthreshold leakage current. In this paper, a new MOSFET device based on the variation of the gate oxide thickness to lower the subthreshold leakage current has been proposed. The TCAD (Technology Computer Aided Design) simulation results show the reduction of the subthreshold leakage current.
Description: NITW
URI: http://localhost:8080/xmlui/handle/123456789/2565
Appears in Collections:Electronics and Communication Engineering



Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.