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http://localhost:8080/xmlui/handle/123456789/2563| Title: | FPGA implementation of multipliers for ECC |
| Authors: | Kodali, Ravi Kishore Gomatam, Prasanth Boppana, Lakshmi |
| Keywords: | Sunar-Koc multiplier ECC |
| Issue Date: | 2015 |
| Publisher: | Proceedings on 2014 2nd International Conference on "Emerging Technology Trends in Electronics, Communication and Networking", ET2ECN 2014 |
| Citation: | 10.1109/ET2ECN.2014.7044939 |
| Abstract: | Scalar Multiplication(SM) is the most frequently used operation in Elliptic Curve Cryptography(ECC). The efficiency of an ECC based system depends on the efficient implementation of SM. The type of basis used while designing a cryptosystem determines the space and time complexities. We implemented two multipliers based on Optimal Normal Basis of type II(ONB) and polynomial basis. This work uses Karatsuba and Sunar-Koc algorithms. The hardware implementations of both the multipliers have been carried out for different key lengths: 243, 251, and 270 bits. The FPGA device used for hardware implementation is XC6VLX240T(Virtex-6). The synthesis results are compared qualitatively in terms of hardware complexities for these key lengths. |
| Description: | NITW |
| URI: | http://localhost:8080/xmlui/handle/123456789/2563 |
| Appears in Collections: | Electronics and Communication Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| FPGA_implementation_of_multipliers_for_ECC.pdf | 158.19 kB | Adobe PDF | View/Open |
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