Power optimized PLL implementation in 180nm CMOS technology

Abstract

This paper describes the design of power optimized phase locked loop for frequency synthesis, Clock and Data recovery, carrier synchronization and many more communication and VLSI applications. PLL consist of Phase Frequency Detector, charge pump along with passive low pass filter and wide tuning VCO. A modified ring oscillator with tuning range of 280 MHz to 2.47GHz and phase noise of -112.4dBc/Hz at 1MHz offset is designed. Frequency Detector consist of DFF along with CMOS gates with low power architectures. Traditional charge pump, passive low pass filter, modified ring oscillator and divider for frequency synthesis offers less power and system noise. PLL proposed here has lock in range from 500MHz to 1GHz with output frequency ranging from 1GHz to 2GHz, maximum pull in time of 244ns and maximum power consumed is 252µW at 2GHz