A 10-bit 25MSPS Low Power Pipeline ADC for Mobile HDTV Receiver System

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DC Field	Value	Language
dc.contributor.author	Dongre, Krushna	-
dc.contributor.author	Akre, Pratik	-
dc.contributor.author	Kamdi, Rahul	-
dc.contributor.author	Sarangam, K.	-
dc.date.accessioned	2025-01-03T05:06:10Z	-
dc.date.available	2025-01-03T05:06:10Z	-
dc.date.issued	2014	-
dc.identifier.citation	10.1109/ECS.2014.6892549	en_US
dc.identifier.uri	http://localhost:8080/xmlui/handle/123456789/2379	-
dc.description	NITW	en_US
dc.description.abstract	This paper describes a 10-bit 25MSPS analog-to-digital converter (ADC) for Mobile HDTV Receiver System. The ADC is based on a 4-3-3 bits- per-stage pipeline architecture and The proposed pipelined ADC adopts a optimized stage resolution based on power consumption of sample and hold circuit and comparator. At the target sampling rate of 25MS/s, measured results show that the converter consumes 12.36mW from a 1.8V power supply and 56dB SNR and 60dB SFDR.	en_US
dc.language.iso	en	en_US
dc.publisher	2014 International Conference on Electronics and Communication Systems, ICECS 2014	en_US
dc.subject	HDTV Receiver,	en_US
dc.subject	Low power	en_US
dc.title	A 10-bit 25MSPS Low Power Pipeline ADC for Mobile HDTV Receiver System	en_US
dc.type	Other	en_US
Appears in Collections:	Electronics and Communication Engineering

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A 10-bit 25MSPS low power pipeline ADC for Mobile HDTV Receiver System.pdf		1.6 MB	Adobe PDF	View/Open