Coherent BPSK demodulator using Costas loop and early-late gate synchronizer

Abstract

The paper presents the design of a digital transceiver with binary phase-shift-keying (BPSK) modulation scheme. The resulting transmitter communicates 4 Kbps data modulating a 128KHz carrier, with receiver sampling frequency of 2MHz. The receiver compensates for frequency and phase errors caused by various sources like clock drifts, Doppler shift and bit-time errors. The Costas loop and Early-Late Gate (ELG) Synchronizer are used for coherent data detection. The simulation has been carried out using MATLAB Simulink and Modelsim PE and each module is verified for its working. Finally the design is implemented on Xilinx Spartan 3 FPGA to verify its behavior in real-time environment.