A Novel on chip LDO voltage regulator in 180nm

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DC Field	Value	Language
dc.contributor.author	Rao, Patri Sreehari	-
dc.contributor.author	Krishnaprasad, K.S.R	-
dc.date.accessioned	2024-12-03T09:07:27Z	-
dc.date.available	2024-12-03T09:07:27Z	-
dc.date.issued	2008	-
dc.identifier.citation	10.1109/ICED.2008.4786685	en_US
dc.identifier.uri	http://localhost:8080/xmlui/handle/123456789/1914	-
dc.description	NITW	en_US
dc.description.abstract	An on chip low drop out voltage regulator that employs a simple fast path and an elegant compensation scheme is presented in this paper. The novelty in this design is that the device parasitic capacitances are exploited for compensation at different loads. The proposed LDO is designed to provide a constant voltage of 1.2V and is implemented in UMC 180 nano meter CMOS technology. The voltage regulator presented improves stability even at lighter loads and enhances line and load regulation while providing reasonably good transient response.	en_US
dc.language.iso	en	en_US
dc.publisher	2008 International Conference on Electronic Design, ICED 2008	en_US
dc.subject	LDO voltage	en_US
dc.subject	voltage	en_US
dc.subject	UMC 180 nano meter	en_US
dc.title	A Novel on chip LDO voltage regulator in 180nm	en_US
dc.type	Other	en_US
Appears in Collections:	Electronics and Communication Engineering

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