Low Power Reconfigurable Sub -Band Filter Bank ASIC for MP3 Decoder

Abstract

There is an ever demanding need to develop low power audio devices using MP3 technology. From the profiled results ofMP3 algorithm on ARMprocessors it has been observed that, the synthesis filter bank in the audio decoder consumes maximum power. Hence to reduce the power consumption ofthe filter bank,· we developed an IEEE 754 single precisionjloating-point runtime re-configurable architecture. The proposed architecture consumes less power at run time as the last 12 bits ofthe mantissa part ofthe synthesis filter coefficients are zero most of the time and hence the corresponding multipliers will be switched off. Since the active multipliers during Inverse Polyphase Quadrature Mirror Filter banks (IPQMF) are less, we are able to achieve low powered decoding process without significantly compromising on the accuracy and speed. We synthesized and simulated the architecture using 0.35 Jim process technology under Synopsys environment. A uniform worst case power reduction of23.7% has been achieved in the frequency range from 1MHz to 20 MHz when all the multipliers are in active state.