http://localhost:8080/xmlui/handle/123456789/385 2026-04-26T08:24:50Z 2026-04-26T08:24:50Z Lakshmi Prasanna, J http://localhost:8080/xmlui/handle/123456789/3499 2025-10-29T10:17:39Z 2024-01-01T00:00:00Z

Title: Novel Absorber Engineering Techniques to Enhance the Efficiency of Perovskite Solar Cells Authors: Lakshmi Prasanna, J Abstract: In recent years, perovskite solar cells have emerged as a promising technology in the field of photovoltaics. However, their efficiency is hindered by various factors that necessitate a comprehensive investigation. This research focuses on absorber engineering, bandgap grading optimization, and the application of machine learning algorithm. By doing so, this study aims to significantly contribute to the advancement of perovskite solar cell technology. This comprehensive thesis undertakes a multifaceted exploration of perovskite solar cells (PSCs), to address crucial challenges and enhance efficiency. The initial investigation reveals performance-limiting parameters in contemporary PSCs, emphasizing deficits in fill factor (FF) and open-circuit voltage (VOC). Absorber characteristics and device optimizations, such as carrier concentration control and shunt resistance considerations, result in a significantly improved device with enhanced VOC, FF, and power conversion efficiency (PCE). A subsequent theoretical study focuses on configurational optimization of heterojunction PSCs to minimize internal recombination, employing various design alterations. The optimized device exhibits noteworthy enhancements in PCE, FF, and VOC compared to benchmark configurations. Moving forward, a proposed bandgap grading profile seeks to maximize spectrum absorption in perovskite absorber material, targeting the Shockley Queisser (SQ) limit. Analyzing linear bandgap grading profiles, the research identifies an optimal range for efficiency, emphasizing a well-optimized small bandgap grading range to achieve 31% power conversion efficiency. Continuing the exploration, a novel double absorber layer structure is introduced, incorporating 12 different absorber layer combinations. This approach expands spectral absorption, mitigates thermalization losses, and achieves an impressive efficiency exceeding 35%. To deepen insights, a dataset of 3490 samples characterizing perovskite structures is generated. Leveraging machine learning with the Random Forest algorithm, a predictive model classifies structures and offers valuable insights into optimized PSC design. Overall, this thesis contributes significantly to the advancement of PSC technology, offering novel solutions, theoretical insights, and practical design guidelines. The findings promise higher PCE and improved overall performance, propelling PSCs toward their potential as a leading photovoltaic technology in the renewable energy landscape. Description: NITW

2024-01-01T00:00:00Z Raveendra, Podeti http://localhost:8080/xmlui/handle/123456789/3498 2025-10-29T10:11:38Z 2024-01-01T00:00:00Z

Title: Exploring Design of Physical Unclonable Functions (PUFs) for Robust Hardware-Assisted Security Authors: Raveendra, Podeti Abstract: Physical unclonable function (PUF) is a promising hardware that augments the security feature for Integrated Circuit (IC) identification and authentication. It is one of the reliable solutions to many security threats as it facilitates die-unique identifier features by increasing uncertainty and prediction. PUF technology, especially for compact IoT enabled devices, makes use of inherent Process Variations (PVs) of ICs attained by chip manufacturers and transforms them into distinctive digital keys to offer a possible solution to security-related issues. Fascinatingly, Machine Learning (ML) is a relatively prominent and inexpensive method that is frequently employed to tackle PUFs. As a result of the PUF’s instability due to environmental changes, additional circuits are now being explored to fix the threats that ensue. In this thesis, we discuss different facets of PUF design with a strong emphasis on the circuit details. From basic PUF designs presented by the researchers, the ultimate design challenges are identified, and prominent solutions are offered that should satisfy the PUF evaluation metrics before contrasting different PUF core implementations. Con cerning the detailed literature, we proposed an XoR Feed Arbiter PUF (XFAPUF) that minimizes vulnerabilities by introducing more complexity in the arbitration process using a relatively smaller number of challenges against conventional Arbiter PUF (APUF). It offers better uniqueness and reliability than prior works as it achieves promising results, such as uniqueness of 50.03%, diffuseness of 49.52%, and worst-case reliability of 99.81% that ranges from 10◦C to 80◦C, with 10% fluctuations in supply voltage (VDD). In ad dition, an enhancement in reliability is achieved by a chaotic-based challenge generation mechanism introduced for feeding APUFs to increase the non-linearity in the arbitration process. Subsequently, an automated challenge-feeding mechanism by Recursive Challenge Abstract viii Feed Arbiter Physical Unclonable Function (RC-FAPUF) is proposed to generate unique, unpredictable, and reliable keys that are independent of the challenges that are gener ally fed by the user. The robustness of the keys is measured by an average reliability of 99.91% and also validated through a lower prediction accuracy of 48% and 52.7% with Linear Regression (LR), and ML classifiers respectively. Furthermore, to power up suit able IoT sub-systems or sensors, a Relaxation Oscillator PUF (ReOPUF) is designed to generate a 4.4MHz frequency along with key generation. The reliability of ReOPUF re sponses has been improved from 95.33% for the conventional Ring Oscillator (RO) PUF to 99.19%. Besides, a Schmitt-Trigger (ST) based APUF instance is introduced that uses PVs in Hysteresis Width (HW) to attain the non-linearity in the Challenge Response Pair (CRP) mechanism. Thereby, impersonation of the responses (keys) is complex perhaps various trials are performed to predict the keys. It offers reliability while achieving 0.15%, and 0.31% Bit Error Rate (BER) concerning the variations in temperature and VDD re spectively. Finally, the proposed PUF designs are implemented in UMC180nm CMOS technology that is suitable for prominent security assistance to IoT-enabled devices and is more resilient against ML attacks Description: NITW

2024-01-01T00:00:00Z PUPPALA, RAVI SANKAR http://localhost:8080/xmlui/handle/123456789/3497 2025-10-29T10:09:09Z 2024-01-01T00:00:00Z

Title: Triboelectric Nanogenerator Device Development, Analysis and Prediction for Energy Harvesting Authors: PUPPALA, RAVI SANKAR Abstract: As the global need for renewable energy sources grows, research into clean and cost effective harvesting of energy devices has become vital. The purpose of this thesis is to explore the design, production, and optimizing of Triboelectric Nanogenerator (TENG) technologies using reusable waste materials. The goal is to limit waste accumulation and boost sustainable energy generation by reusing materials. The current thesis focuses on the use of reusable material aluminium foil as an electrode in a device. As a dielectric material, the gadget used a laboratory film known as Parafilm, which the researchers compared to other low-cost materials such as OHP, PET, and PMMA. created several Triboelectric Nanogenerator (TENG) architectures and observed that the output response improved significantly from 4 V to 200 V. This enabled the TENG to power tiny devices such as digital watches, calculators, thermometers, and even LEDs containing up to 85 LEDs. To validate the practical results, with the help ofsimulation platform called COM SOL tool, by considering various parameters for simulation, such as the hardware design materials, their thickness, and properties, keeping them consistent with the practical setup. The simulation results closely matched the practical findings, reinforcing the accu racy of their experiments. To further improve the prediction of output power for unknown load conditions, incorporated algorithms for to reduce the loss in the accuracy prediction used deep learning and machine learning algorithms. In Machine learning random forest regression and in deep learning Adamdelta is giving less loss compared to existing algo rithms. The outcome of this research lead to reduce the waste materials and helpful to the society in terms of air, water, and soil pollution. The proposed research offers the design of TENG device with less cost, validate the practical results with simulation results with scaling factor and for the complex designs to predict the output power for unknown load conditions using AI Description: NITW

2024-01-01T00:00:00Z Lakshmi Kiranmai, V. http://localhost:8080/xmlui/handle/123456789/3496 2025-10-29T10:05:46Z 2024-01-01T00:00:00Z

Title: Design and evaluation of scalable 2D, 3D and hybrid interconnects for Network-on-Chip Authors: Lakshmi Kiranmai, V. Abstract: Network-on-Chip (NoC) is an emerging and efficient on-chip interconnect technology. NoC is a viable option to design modular, scalable, robust communication interconnect architectures. Topology is one among many crucial design aspects of NoC, as it affects the performance of the interconnection network. Mesh is the most extensively used and favoured architecture for implementing less sophisticated SoCs due to its simple, scalable, regular structure, low-radix routers and short-range links. However, as the network scales, Mesh suffers from degraded performance because of large diameter. The present work aims at developing efficient and scalable novel topologies– 2D, 3D topology, hybrid wired topology and hybrid wired-wireless topology for on-chip interconnect architectures that outperform Mesh topology. The objectives of the research are threefold– First, to design a hybrid wired topol ogy i.e., combining two topologies. Second, to design a diagonal Mesh based topology by inserting diagonal links into the conventional Mesh topology retaining the simple, scalable, regular structure of Mesh simultaneously improving the performance. Third, to design a three-level hierarchical hybrid wired-wireless interconnection architecture for large networks. To begin, the present work proposes a novel, scalable, hybrid Hexagonal Star (HS) topology for on-chip connectivity networks. The proposed topology’s properties have been investigated and compared to those of the Mesh, Torus, and Honeycomb Mesh topologies. The performance of the Hexagonal Star topology has been studied and compared to that of the Mesh topology in different scenarios. The comparative studies of topological properties have indicated that the proposed topology can be a potential choice for on-chip interconnection networks. For different traffic patterns and traffic loads, HS topology has registered a reduction of packet latency ranging from 15% to 50% and from 9% to 23% for Abstract vii 18 nodes and 32 nodes, respectively, compared to Mesh topology. Further, the synthesis results indicate a significant reduction of area consumed by HS topology compared to the area consumed by an identically configured Mesh topology. Second, the present work proposes DiamondMesh, an area and energy efficient diag onal mesh based topology. By incorporating diagonal links into the basic mesh topology, the proposed DiamondMesh increases network performance while keeping the Mesh topol ogy’s regular, simple, and scalable features. Topological properties of DiamondMesh have been explored and compared with that of other competitive diagonal mesh topologies. The proposed topology and other state-of-the-art diagonal Mesh topologies have been simulated and synthesised. The evaluation results indicate that there has been a signifi cant reduction of latency compared to Mesh and other diagonal mesh topologies except DMesh and a considerable reduction of area and power compared to the DMesh topology. Finally, in order to address the limitations of electrical interconnects, the current work investigated hybrid wired-wireless topologies. Three-level hierarchical hybrid wired wireless Network-on-Chip (NoC) designs have been proposed and evaluated under differ ent traffic patterns at low, medium, and high traffic loads. In the proposed three-level hierarchy, the bottom and top levels are concerned with subnet topology and wireless hub topology, respectively. The present research introduces a middle level that investigates the number of nodes that will be connected to a subnet’s wireless hub. Mesh and fully connected wireless topologies have been chosen for the bottom and top levels of the hi erarchy, respectively. Different hybrid wired-wireless configurations have been developed and studied by varying the number of subnets and the number of nodes to be attached to the subnet at the middle level. The objective of investigating the middle level is to reduce the number of subnets and, consequently, the number of wireless nodes in large network architectures without compromising performance. The proposed hybrid archi tectures outperform baseline wired Mesh architecture in terms of latency and throughput characteristics. Description: NITW

2024-01-01T00:00:00Z