Browsing by Author Murthy, N.S.
Showing results 1 to 8 of 8
| Issue Date | Title | Author(s) |
| 2013 | A closed-form delay estimation model for current-mode high speed VLSI interconnects | Kavicharan, M; Murthy, N.S.; Rao, N. Bheema |
| 2013 | Digital beam former architecture for sixteen elements planar phased array radar | Rao, D. Govind; Deshpande, Aalhad P.; Murthy, N.S.; Vengadarajan, A |
| 2011 | An Efficient Architecture for H.264 Intra Prediction Mode Decision Algorithm | Muralidhar, P.; Devi, R.V.; Rao, C.B.R; Murthy, N.S. |
| 2013-08 | An efficient delay estimation model for high speed VLSI interconnects | Kavicharan, M.; Murthy, N.S.; Bheema Rao, N. |
| 2012-03 | Fully parallel and fully serial architecture for realization of high speed FIR filters with FPGA's | Sudhakar, V.; Murthy, N.S.; Anjaneyulu, L. |
| 2009 | Identification of LPI Radar Signals by Higher Order Spectra and Neural Network Techniques | Anjaneyulu, L.; Murthy, N.S.; Sarma, N.V.S.N. |
| 2008 | Radar Emitter Classification Using Self-Organising Neural Network Models | Anjaneyulu, L.; Murthy, N.S.; Sarma, N.V.S.N. |
| 2014 | Transient Analysis of VLSI Tree Interconnects based on Matrix Pade Type Approximation | Kavicharan, M; Murthy, N.S.; Bheema Rao, N. |
